High speed serrodyne digital frequency translator

ABSTRACT

A high-speed serrodyne digital frequency translator utilizes a digital phase-shifter, for example, of series coupled Schiffman type cells, which have reference and delay paths which are switched by three-terminal devices of the gallium arsenide FET type. No bias voltages are used and the FETS are driven by the output of a binary divider network which in turn is composed of GaAs FETS as active elements. Thus switching in the picosecond range results.

This is a continuation of application Ser. No. 797,149 filed Nov. 12,1985 now abandoned.

BACKGROUND OF THE INVENTION

The present invention is directed to high speed digital phase shiftingapparatus and more particularly to digital frequency translation usingthe serrodyne principle.

Fast phase shifters are required in several areas particularly in theradar and Electronic Counter Measures (ECM) fields. In general, thephase shifters use a serrodyne system where swift phase changes resultin nearly pure sideband generations. Serrodyning is a prevailing ECMtechnique used to prevent continuous wave (CW) or doppler trackingradars from gaining accurate velocity information. Such a system isshown in co-pending application, Ser. No. 534,566, filed Sep. 22, 1983,in the names of Asad M. Madni and Joseph Fala (Asad M. Madni is one ofthe co-inventors of the present application), entitled: "VELOCITYDETECTION APPARATUS". The disclosure of the Madni/Fala application ishereby incorporated by reference.

That application discloses a digital phase-shifter which produces aslowly changing false doppler frequencies. Thus, it performs a velocitygate stealer (VGS) function. VGS pulls the velocity tracker off thetarget return and drops it. The radar may then lock on to clutter or beforced into a reacquisition sequence. Typical frequency translations forthe VGS function are between 20 Hz and 200 KHz which, for a 32-stepoperation implies clock frequencies of 6.4 MHz. Since the phase shiftermust switch at least twice this rate, this implies a necessary switchingfrequency of 12.8 MHz or switching time of less than 20 nsecs. Asdisclosed in the above co-pending application, the switching time is metby, for example, utilizing a digital phase-shifter of the Schiffman typewhere each cell of the phase-shifter is driven by an output of amulti-bit counter whose clock input in turn is driven by avoltage-to-frequency converter which has a pulse train output. Each cellof the digital phase-shifter is sequentially switched in and out of thephase-shifter circuit by diode switches as disclosed in theabove-mentioned pending application. Such diode switches may typicallybe of the PIN type (meaning P and N semi-conductor materials separatedby an intrinsic layer). Typical switching speeds of PIN diodes are 10nsecs with 2 to 3 nsecs achievable in some applications. Thus, PIN diodeswitches are very adequate for the foregoing requirement.

Another type of phase-shifter which can be utilized is a varactorphase-shifter. However, this requires a digital to analog converter. Incombination with the limitations of the above conversion and thenon-linearities in the varactor diode itself, a varactor typephase-shifter suffers from poor accuracy, complexity and limited speed.In contrast a digital computer can drive a fully digital phase-shifterdirectly.

In addition to doppler and CW radar, there is a pulse compression radarwhich goes under the acronym CHIRP. Here, a gate stealer ECM techniquecan be generated in exactly the same manner as a velocity gate stealingtechnique, in that a range tracker is pulled off the true target returnand then dropped. This, however, with use of a digital phase-shifterimplies switching times in the order of pico-seconds. Such short timesare not achievable using PIN diodes as switching elements.

OBJECT AND SUMMARY OF THE INVENTION

It is a general object of the present invention to provide an improvedhigh-speed serrodyne digital phase-shifter.

In accordance with the above object, there is provided a phase-shifterapparatus for receiving radar or other microwave signals andphase-shifting or frequency translating them comprising a solid statevariable phase-shifter including a plurality of series coupled cells forinserting various and different phase shifts into the received microwavesignals by binary inputs to selected cells. Each of the cells providesat least two expected phase shifts, one of which may be zero degrees, sothat driving said binary inputs with an incrementally increasing binarynumber will cause step increases in expected phase shift of the seriescombination of the cells.

Each of the cells includes switching means responsive to a binary inputfor causing the cell to have one of the expected phase-shifts. Theswitching means includes at least a three-terminal gallium arsenidefield effect transistor (GaAs FET) having no d.c. bias and a gate inputwhich is driven by the binary input.

Multi-bit counter means are provided which have a number of binaryoutputs corresponding to the binary inputs of the plurality of cells forproviding the binary number. Means are provided for digitally drivingthe counter means.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of apparatus incorporating the presentinvention.

FIG. 2 is a timing diagram illustrating the operation of the invention.

FIG. 3 is a simplified block diagram illustrating the operation of FIG.1.

FIG. 4 is a simplified plan view of a phase-shifter portion of FIG. 1.

FIG. 5 shows the switching circuits portion of FIG. 4.

FIGS. 6A and 6B show two different conditions for the switches utilizedin FIGS. 4 and 5.

FIG. 7 shows the characteristic curve of the switches in FIGS. 6A and6B.

FIGS. 8A, 8B and 8C are typical equivalent electrical circuits of theswitch of FIGS. 6A and 6B.

FIGS. 9A through 9D show alternative embodiments of digitalphase-shifters useful in the present invention.

FIGS. 10A and 10B illustrate a series mode operation.

FIGS. 11A and 11B illustrate a shunt mode operation.

FIG. 12 is a plan view illustrating the phase-shifter of FIG. 9B for a90° cell.

FIG. 13 is a simplified plan view illustrating the phase-shifter of FIG.9C.

FIG. 14 is a circuit schematic of one of the divide-by-two units of FIG.1.

DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 illustrates the basic circuit for accomplishing the serrodyningtechnique of the present invention. This is, of course, a phasemodulation using the transit time modulation of the phase-shifter. Asillustrated, phase-shifter 11 is a solid-state digital phase-shifterwhich consists of five sections or cells which can be switched in andout of a series path to insert various and different phase shifts intothe radio frequency (RF) circuit. It should be noted that in the presentinvention the RF frequencies with the CHIRP type of radar would be inthe gigahertz range. The radio frequency input is received at one end ofthe phase-shifter (RF input), phase-shifted and outputted at the otherend (RF output). Within each of the five cells 11a through 11e, there isindicated the respective phase-shift; viz: 111/4°, 221/2°, 45°, 90° and180°. The cells are driven by a multi-bit counter 12, which is in theform of a binary divider network, the counter 12 being driven by a clock13 having an offset frequency adjustment 14. The output of each unit ofcounter 12, that is 12 a to 12e (which may be merely flip-flopcircuits), is coupled to phase-shifter 11 by driver pairs 16 which maybe diodes or FETs. These binary inputs to the phase-shifter serve thepurpose of turning the individual units on and off.

This overall functioning is illustrated in FIG. 2 which shows eachindividual cell of the phase-shifter 11 designated by its number ofdegrees of phase-shift as it is driven by the counter 12. Normally, thecounter counts up an incrementally increasing binary number which causesa step increase in the expected phase-shift of the series combination ofcells as indicated by the stepped curve 17. In this case since it is afive-bit phase-shifter, there are 32 steps. Frequency translation takesplace over one period of the translation frequency. Thus, for 32-stepoperation, the clocking frequency of clock 13 must be 32 times thistranslation frequency. Thus, it is apparent that in the CHIRP type ofradar, the phase-shifter which switches at approximately twice the aboverate must operate in the pico-second range. Any time delay of theswitching of the individual cells of the phase-shifter will result inundesired amplitude notching of the output due to switching crossoverdropouts in the switch. This results in amplitude modulation componentsat the clock frequency on the spectrum. The present invention byreducing the delay time of the above switching, eliminates suchdeleterious side effects.

FIG. 3 illustrates the foregoing operation in simplified format, wherethe various cells 11a-11e of the phase-shifter are illustrated, which intheir preferred embodiment may be of the Schiffman type. Here in one ofphase delay modes, there is a zero degree phase-shift and as indicatedanother designated phase-shift. The input control bits are onlyindicated schematically as one line control which control the state ofthe cell in a manner as illustrated in FIG. 2.

FIG. 4 illustrates in detail a typical Schiffman type cell, for example,11c and a portion of an adjacent cell 11b. Referring to cell 11c, thereis a reference path 21, meaning a nominal zero degree phase-shift, andalso a delay or adjustment path 22 which, for example, might be 90°.This cell is switched between these two conditions by the switchingpairs, Q1, Q2 and Q3, Q4. This is better illustrated in FIG. 5. Theseswitches are naturally a key link in the overall pico-second speed ofthe circuit. As will be discussed in further detail below, they aregallium arsenide, field effect transistors (GaAs FET). Such a GaAs FETcan switch at a very high speed with a transition time of around 150pico-seconds. In addition, no power is required to drive their gates,and no bias is required on the drain or source. As indicated clearly inFIG. 5, the specific connection of each GaAs FET is that of athree-terminal device with the drain and source connected between eitherthe delay path 22 or the reference path 21. These switches are driven bythe binary outputs of counter (divider) 12.

Since no d.c. bias is required on switches Q1-Q4, the adjacentphase-shift cell 11b, as shown in FIG. 4, may be directly connected,without the need of an isolating capacitor, to the cell 11c.

Referring to the FIGS. 6A and 6B, these illustrate a cross-section ofthe GaAs FET in "on and off" states, respectively. As is apparent, it isa three-terminal device with a source, a drain and a gate terminal. Agate voltage V_(G) controls the switched state. In a typical switchmode, the high impedance or off state corresponds to a negative gatebias, higher in magnitude than the pinch-off voltage Vp. This isillustrated in FIG. 8B. FIG. 8A shows the on-condition which is alow-impedance state (1 to 3 ohms, for example). Here the gate voltageis, of course, less than pinch-off voltage. In either state virtually nod.c. bias power is required.

FIG. 7 illustrates the two "on and off" operating regions of the GaAsFET. It is apparent that the operating regions are very linear.

In the "on" state (FIG. 6A), the device can be modeled as a linearresistor, as illustrated in FIG. 8A. The capacitance is minimal andtypically of the range of 0.1 pF to 0.3 pF. When a negative gate voltageis applied between gate and source so that it is greater than thepinch-off voltage, the channel underneath the gate can be depleted ofcharge carriers as illustrated in FIG. 6B. In the "off" condition, thefield effect transistor can be modeled as a resistor, capacitorcombination, as illustrated in FIG. 8B. Here, the "off" resistance istypically 2 kilohms to 20 kilohms. Finally, the gate circuit equivalentis shown in FIG. 8C as a series capacitor of 0.1 pF to 0.3 pF and aresistor of 2 ohms to 20 ohms. Switching occurs only through the gatecontrol voltage and no other bias is required. In view of the gatecircuit of FIG. 8C, the gate current is either zero or negligible. TheFET switching time can be estimated from the equivalent gate circuit ofFIG. 8C. With the nominal values of resistance and capacitance shown,the charging time constant is approximately 50 pico-seconds.

Various digital phase-shifters, in addition to the Schiffman type, maybe utilized with the gallium arsenide FET switch of the presentinvention. FIG. 9A illustrates in very simplified form a switched linephase-shifter circuit (which is equivalent to a Schiffman cell) andwhich has in effect 2 single-pole double-throw switches 31 and 32. Thispermits either one of two paths to be selected as a transmission path.In the context of the Schiffman type cell, one path would be thereference of zero degree path, and the other the delay path. The formulafor the amount of phase-shift ΔΦ is illustrated in conjunction with thediagram. In the actual Schiffman cell, as schematically illustrated inFIG. 5, rather than utilizing the single-pole double-throw switches,pairs of GaAs FETS are utilized with their gates tied together.

Next in complexity is a reflection type phase-shifter illustrated inFIG. 9B. When switch 33 is closed, the plane of reflection is in theplane of the switch; when the switch is open, the plane of reflection isat the short. A circulator 34 is also a part of the circuit.

In general, all phase-shifter cells or "bits" can be implemented usingFET's in a shunt mode configuration or a series mode configuration.

In the series mode, as illustrated in FIGS. 10A and 10B, the signal pathis between the FET source and drain which can be made to open (highresistance) or close (low resistance) by applying gate voltage. FIG. 10Bis, therefore, equivalent to the Schiffman cell 11c and its FET switches21-24 of FIGS. 4 and 5. However, this can be implemented in the shuntmode also.

In the shunt mode, as illustrated in FIGS. 11A and 11B, the FET (viz:Q1'-Q4') is placed across the signal path (drain connection)to theground (source connection). Turning the FET on by means of the gate,produces a low resistance from drain to source effectively shorting thesignal to the ground. Used in conjunction with quarter wavelengthtransmission lines (see FIG. 11A), this short produces an open circuitat the RF input to the switch. Thus, referring to FIG. 11A, path 22would be open and path 21 closed (where switches Q3' and Q4' are off).

FIG. 12 shows an actual physical layout of the 90° cell of a reflectiontype phase-shifter (FIG. 9B). It includes a Lange coupler 36, plus apair of gallium arsenide FETS 37 and 38, with the source terminalgrounded. Therefore, this is a shunt mode operation.

FIG. 9C shows a loaded transmission line type phase-shifter, where whenshunt inductors are switched in by switches 39 and 41, phase velocity isincreased. The quarter wavelength path between the elements causes apartial cancellation of their mis-matches. When the capacitor legs areswitched in, phase velocity is reduced causing additional phase delay.An actual physical representation of such a loaded line shifter is shownin FIG. 13 where the switches 39 and 41 are gallium arsenide FETS withtheir source terminal grounded.

The fourth type of digital phase-shifter is illustrated in FIG. 9D whichis of the Hi-Low pass type. The circuit elements are selected so thatthe T circuit is exactly matched, whether the switches are in a positionto form a low-pass circuit or a high-pass circuit. There are three pairsof inductive-capacitive legs which are switched by the schematicallyindicated switches 42, 43 and 44, each of which would be replaced by apair of GaAs FET switches. Thus, six GaAs FETS would be required forswitching between the inductive capacitive pairs.

The rapid pico-second magnitude switching times of the phase-shifter 11illustrated in FIG. 1, can only be obtained if the counter or binarydivider network 12 has an equivalent switching time. This can beaccomplished by use of GaAs FET switches in each of the flip-flop units12a through 12e. FIG. 14 illustrates a standard figuration of a singleunit, for example, flip-flop unit 12a, which includes 4 gallium arsenideFETS Q1 through Q4, which are actuated by a select line 46 and have thetwo output lines 47 and 48. These are equivalent to the lines whichdrive the diode drivers 16 of FIG. 1.

Besides speed, another advantage of the use of GaAs FET switches is thatthey, as a group, are integratable on one monolithic substrate. Thisagain cuts delay times and increases speed. Also the GaAs FETS can beoptimized for low pinch-off voltage to minimize gate swing and videoswitching spike leakage.

The GaAs FET switches can be implemented using several different typesof FETS. This includes depletion mode metal, enhancement mode metal, andhigh electron mobility transistors, sometimes called modulation-dopedFETS. The first two have gate delays of 50 to 100 pico-seconds, and thelast a gate delay of 3 to 6 pico-seconds.

Thus, the present invention provides a very high speed serrodyne digitalfrequency translator by the use of three-terminal GaAs FET devices whichheretofore have only been utilized as analog microwave amplifiers, forexample. Since no d.c. bias is necessary, they are eminently suitablefor use in digital phase-shifter applications, in that no couplingcapacitors are necessary.

What is claimed:
 1. Serrodyne phase-shifter apparatus for receivingradar or other microwave signals and phase shifting or frequencytranslating them comprising:a solid-state variable phase shifterincluding a plurality of series coupled cells for inserting various anddifferent phase-shifts into said received microwave signals by binaryinputs to selected cells, each of said cells providing at least twoexpected phase shifts, one of which may be zero degrees, so that drivingsaid binary inputs with an incrementally increasing binary number willcause step increases in expected phase shift of the series combinationof the cells; each of said cells including switching means responsive toa said binary input for causing such cell to have one of said twoexpected phase-shifts, swid switching means including a plurality ofthree terminal gallium arsenide field effect transistors (GaAs FET)having no d.c. bias and a gate input which is driven by said binaryinput and source and drain terminals, said switching means including afirst pair of said FETs, having a common gate input for providing one ofsaid two expected phase shifts by forming a conductive path for saidsignals between said source and drain terminals and a second pair ofsaid FETs, having a common gate input for providing another of said twoexpected phase shifts by forming a conductive path for said signalsbetween said source and drain terminals; multi-bit counter means havinga number of binary outputs corresponding to said binary inputs of saidplurality of cells for providing said binary number; and means fordigitally driving said counter means.
 2. Apparatus as in claim 1, wheresaid counter means includes series connected flip-flop circuits, eachwith a pair of gallium arsenide FETS.
 3. Apparatus as in claim 2including clock means for driving said counter means.
 4. Apparatus as inclaim 1, where said cells are of the Schiffman type including referencepath and a delay path and where said switching means alternately seriesconnect such lines in response to said binary inputs.
 5. Apparatus as inclaim 1, where said cells are of the reflective type and said FETS havea source terminal grounded.
 6. Apparatus as in claim 1, where said cellsare of the loaded line type including inductive and capacitive legs andsaid FETS are connected as a pair to provide alternate switching betweensaid legs.
 7. Apparatus as in claim 1, where said cells are of theHi-Low pass type having three pairs of inductive-capacitive legs andwhere six of said FETS provide switching between said pairs. 8.Apparatus as in claim 1, where said cells are d.c. coupled to eachother.